This blog post is about our current EV3 robot we're planning to use in the 2023/2024 FLL competition. Some features: 2 large motors for steering. 2 medium motors for attachments. 2 colour sensors for picking up the white and black lines, also used for line squaring. 1 gyro sensor. To enable attachments to be changed as quickly as possible we're using gravity to keep the gears connected, i.e. you don't need to fasten anything to the robot. Every attachment has 2x 12 tooth double bevel gear (part 32270) which comes in contact with the 2x 20 tooth double bevel gears (part 32269) on the robot. The medium motors are horizontally aligned on the robots, but we use 12 tooth double bevel gears to convert that to vertical alignments. These in turn are connected to 20 tooth double bevel gears, and the attachments in turn connect to these 20 tooth double bevel gears with their 12 tooth double bevel gears. The complete robot is modelled in Bricklink Studio 2 . You can download the rob
Compare this schematic to the 8051 schematic posted earlier.U6 (2764 8kb ROM chip) was replaced with a 6264 8kB SRAM chip. The idea is that the 8051 will still be able to access this chip as an external ROM chip using PSEN#, but also as external RAM. This way it is possible to download firmware to SRAM and execute the firmware as if it was stored on ROM.
Comparing the DIP pinouts between SRAM (6264 8kb SRAM) and ROM (2764 8kB ROM), we can see that the two chips follow more or less the same pin layout, except for the address pins:
| Pin | SRAM | ROM |
| 1 | N/C | Vpp |
| 2 | A4 | A12 |
| 3 | A5 | A7 |
| 4 | A6 | A6 |
| 5 | A7 | A5 |
| 6 | A8 | A4 |
| 7 | A9 | A3 |
| 8 | A10 | A2 |
| 9 | A11 | A1 |
| 10 | A12 | A0 |
| 11 | D0 | D0 |
| 12 | D1 | D1 |
| 13 | D2 | D2 |
| 14 | Gnd | Gnd |
| 15 | D3 | D3 |
| 16 | D4 | D4 |
| 17 | D5 | D5 |
| 18 | D6 | D6 |
| 19 | D7 | D7 |
| 20 | CE1# | CE# |
| 21 | A0 | A10 |
| 22 | RD# | G# |
| 23 | A1 | A11 |
| 24 | A2 | A9 |
| 25 | A3 | A8 |
| 26 | CE2 | N/C |
| 27 | WR# | P# |
| 28 | Vcc | Vcc |
To enable the SRAM to respond to ROM access and RAM access, we need to add logic to the chip select and output enable pins.
Chip select (CE1# and CE2):
The SRAM should be selected either when we have a write (WR#) or read (RD#) to the SRAM segment or when we have a ROM read (PSEN# - Program Store Enable). Referring back to the schematics, we can use any one of CS1# to CS7# of the multiplexer as an enable line for the SRAM segment (note that the other SRAM module is using CS0#). For this example we'll take CS7#, i.e. the external data mapped to the upper 8kB of the 64kB address space will also be used as ROM. This means we must select the chip when either CS7# or PSEN# is active.
CE1 = CS7 OR PSEN
Converting this to negative logic, the OR gate is changed into an AND gate (see U3):
CE1# = CS7# AND PSEN#
CE2 can be tied to Vcc.
Output Enable (PSEN# and RD#): The SRAM must output data on the data bus whenever PSEN# is active or when we have a RD# on the correct SRAM segment. However, the selecting of the SRAM segment is done by the multiplexer (U2), so the output enable should be active on a external data read (RD) or external ROM read (PSEN).
OE = RD OR PSEN
Converting this to negative logic, the OR gate is changed into an AND gate (see U3):
OE# = RD# AND PSEN#
SRAM on an existing ROM socket
It is possible to use an existing ROM socket on a PCB to use a SRAM chip, provided you have easy access to WR#, RD# and CS7# in the vicinity of the ROM socket. Most of the ROM pins can be used as is. Even the address pins can be used as is although the pins differ. As long as the SRAM stores the data at a specific location and is able to retrieve that data at the same location, everything should be fine. Pins 1, 20, 22, 26 & 27 must be modified as per the schematic above.
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