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FLL EV3 Robot

This blog post is about our current EV3 robot we're planning to use in the 2023/2024 FLL competition. Some features: 2 large motors for steering. 2 medium motors for attachments.  2 colour sensors for picking up the white and black lines, also used for line squaring. 1 gyro sensor. To enable attachments to be changed as quickly as possible we're using gravity to keep the gears connected, i.e. you don't need to fasten anything to the robot. Every attachment has 2x 12 tooth double bevel gear (part 32270) which comes in contact with the 2x 20 tooth double bevel gears (part 32269) on the robot. The medium motors are horizontally aligned on the robots, but we use 12 tooth double bevel gears to convert that to vertical alignments. These in turn are connected to 20 tooth double bevel gears, and the attachments in turn connect to these 20 tooth double bevel gears with their 12 tooth double bevel gears.  The complete robot is modelled in Bricklink Studio 2 . You can download the rob
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8051 Schematic with ROM & SRAM



U1: ATMEL 89C52 running at 11.0592 MHz (for standard baud rate generation)
Port 0 is the multiplexed address / data bus. Because this port uses open drain logic, all lines must be pulled high.
Port 1 is not used in this example, can be used for any TTL logic.
Port 2 is used for the upper 8 bits of the address bus.
Port 3 is used for control signals, more specifically the RS232 port and RD# / WR# signals used for external memory reads / writes.

U2: 74HC138 3-to-8 multiplexer
This multiplexer is used to divide the 64 kB RAM address space in 8 x 8kB segments using the upper 3 bits of the address bus. The mutiplexer is only active when WR# or RD# is active, i.e. a write to or read from RAM is active.

U3: 74HC08 AND gate
This AND gate is used to enabled the multiplexer whenever WR# or RD# is active. The WR# and RD# signals uses negative logic (active when at ground) and are multual exclusive (only one can be active at any given time). Note that a positive logic AND gate can be used for a negative logic OR gate.

U4: 74HC573 3-state latch
This latch is used to demultiplex the address bus from the multiplexed address/data bus. The 8051's ALE (Address Latch Enable) drives this latch.

U5: MAX232 RS232 driver
This line driver is used to convert TTL signals (gnd / 5V logic) to valid RS232 signals (+/- 9V).

U6: 2764 8kB ROM
The ROM chip places its data on the data bus whenever the 8051's PSEN# signal is active.

U7: 6264 8kb SRAM
The SRAM is set up using CS0# of the 74HC138 multiplexer, i.e. active for the lower 8 kB range.

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